Instruction Processing

B

Barrel processor
Berkeley RISC
Branch misprediction
Branch predication
Branch predictor
Branch target predictor
Bubble (computing)
Burroughs large systems instruction set

C

CEVA-X DSP
Complex instruction set computer
Control store
Instruction cycle
Cycles Per Instruction

D

DLX
Data dependency
Decimal mode
Decoupled architecture
Degree of parallelism
Delay slot

E

Execution (computers)
Explicitly parallel instruction computing

H

Hazard (computer architecture)

I

Instruction level parallelism
Instruction set
Instruction set matrix
Instructions Per Cycle
Interlock (engineering)
Itanium

J

Jazz DSP

M

MIL-STD-1750A
MIPS architecture
Memory barrier
Micro-operation
Microarchitecture
Microcode
Minimal instruction set computer
Model-specific register
Multithreading (computer hardware)

N

Native mode

O

Orthogonal instruction set
Out-of-order execution

P

Instruction pipeline
Pipeline (computer)
Classic RISC pipeline
Instruction prefetch
Prefetch input queue

R

Re-order buffer
Reduced instruction set computer
Register window
Reservation stations
Reset vector

S

ST200 family
Slipstream (computer science)
Speculative execution

T

Tomasulo algorithm
TriMedia

U

User:Cbaek/tomasulo algorithm

V

Very long instruction word

Z

Zero Instruction Set Computer

Fonte: Wikipedia